Design of Sequential Elements for Low Power Clocking System
Design of Sequential Elements for Low Power Clocking System
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DOI：
10.1109/tvlsi.2009.2038705
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发表时间：
2011-05
影响因子：
2.8
通讯作者：
P. Zhao;J. McNeely;W. Kuang;Nan Wang;Zhongfeng Wang
中科院分区：
文献类型：
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作者：
P. Zhao;J. McNeely;W. Kuang;Nan Wang;Zhongfeng Wang
功耗是系统性能的主要瓶颈，在2008年国际半导体技术路线图中被列为三大挑战之一。在实际应用中，由时钟分配网络和触发器组成的时钟系统消耗了芯片上很大一部分功率。本文综述了低功耗时钟系统的各种设计技术。其中一种有效的方法是通过减少时钟晶体管的数量来减小时钟负载的容量。为了解决这个问题，我们提出了一种新的时钟对共享触发器，它将本地时钟晶体管的数量减少了大约40%。时钟驱动功率降低24%。此外，低摆幅和双边时钟，可以很容易地纳入到新的触发器，以建立时钟系统。
Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, we propose a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems.