Sub-1-v design techniques for high-linearity multistage/pipelined analog-to-digital converters
Sub-1-v design techniques for high-linearity multistage/pipelined analog-to-digital converters
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DOI：
10.1109/tcsi.2004.839532
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发表时间：
2005-01-01
影响因子：
5.1
通讯作者：
Moon, UK
中科院分区：
文献类型：
--
作者：
Chang, DY;Ahn, GC;Moon, UK
介绍了一种采用运放复位开关技术的超低电压多级（两级算法）模数转换器（ADC）的设计。一个高度线性的输入采样电路适应真正的低压采样从外部输入信号源。采用基于基数的数字校准技术，在低电源电压下补偿元件失配和降低运放增益。基于基数的方案基于半参考倍增数模转换器结构，其中参考和输入信号路径所看到的误差源对于给定级是相同的。原型ADC采用0.18 μ m CMOS工艺制作。原型集成电路在0.9 v电源下耗散9 mW，输入信号范围为0.9 Vp-p差分。ADC的校准将信噪加失真比从40提高到55 dB，无杂散动态范围从47提高到75 dB。
The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-mum CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 Vp-p differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.