Post-Fabrication Microarchitecture
Post-Fabrication Microarchitecture
复制标题
DOI：
10.1145/3466752.3480119
复制
发表时间：
2021-10
期刊：
影响因子：
--
通讯作者：
C. Kumar;Anirudh Seshadri;A. Chaudhary;Shubham Bhawalkar;Rohit Singh;E. Rotenberg
中科院分区：
文献类型：
--
作者：
C. Kumar;Anirudh Seshadri;A. Chaudhary;Shubham Bhawalkar;Rohit Singh;E. Rotenberg
在超标量处理器设计中，通常可以提高许多工作负载性能的微架构增强受到青睐。以一般性能为目标是必要的，但它也限制了一些微架构创新。我们探索通过一种称为后期制造微架构（PFM）的新范例来缓解这一限制。高性能超标量核心与可重构逻辑结构 RF 相结合。可编程接口或代理允许 RF 观察超标量核心的关键管道阶段并在微架构上进行干预。特定于应用的新微架构组件根据 RF 需求进行合成。所有指令仍然像往常一样流经超标量管道，但通过 RF 的微架构干预，它们的执行得到了简化（每个周期更好的指令 (IPC)）。我们的研究表明，通过分析单个应用程序的瓶颈并提供针对这些瓶颈的定制微架构解决方案，可以实现单个应用程序的大幅加速。本文探讨的 PFM 用例示例包括自定义分支预测器和数据预取器。
Microarchitectural enhancements that improve performance generally, across many workloads, are favored in superscalar processor design. Targeting general performance is necessary but it also constrains some microarchitecture innovation. We explore relieving this constraint, via a new paradigm called Post-Fabrication Microarchitecture (PFM). A high-performance superscalar core is coupled with a reconfigurable logic fabric, RF. A programmable interface, or Agent, allows for RF to observe and microarchitecturally intervene at key pipeline stages of the superscalar core. New microarchitectural components, specific to applications, are synthesized on-demand to RF. All instructions still flow through the superscalar pipeline, as usual, but their execution is streamlined (better instructions per cycle (IPC)) through microarchitectural intervention by RF. Our research shows that one can achieve large speedups of individual applications, by analyzing their bottlenecks and providing customized microarchitectural solutions to target these bottlenecks. Examples of PFM use-cases explored in this paper include custom branch predictors and data prefetchers.