Evolution of the Samsung Exynos CPU Microarchitecture

Evolution of the Samsung Exynos CPU Microarchitecture
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DOI：
10.1109/isca45697.2020.00015
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发表时间：
2020-05
期刊：
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
影响因子：
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通讯作者：
B. Grayson;J. Rupley;Gerald D. Zuraski;Eric Quinnell;Daniel A. Jiménez;T. Nakra;P. Kitchin;Ryan Hensley;Edward Brekelbaum;Vikas Sinha;A. Ghiya
B. Grayson;J. Rupley;Gerald D. Zuraski;Eric Quinnell;Daniel A. Jiménez;T. Nakra;P. Kitchin;Ryan Hensley;Edward Brekelbaum;Vikas Sinha;A. Ghiya
中科院分区：
其他
文献类型：
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作者：
B. Grayson;J. Rupley;Gerald D. Zuraski;Eric Quinnell;Daniel A. Jiménez;T. Nakra;P. Kitchin;Ryan Hensley;Edward Brekelbaum;Vikas Sinha;A. Ghiya

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三星Exynos的核心家族是在2011年底从三星奥斯汀研究与设计中心（SARC）开发的高性能“大”处理器。本文讨论了这些核心的微体系结构的选定方面 - 特定于基于感知的分支机构的预测，Specter V2，Specter v2安全性增强，微型操作缓存算法，预摘要的进步和内存延迟优化。
The Samsung Exynos family of cores are highperformance “big” processors developed at the Samsung Austin Research & Design Center (SARC) starting in late 2011. This paper discusses selected aspects of the microarchitecture of these cores - specifically perceptron-based branch prediction, Spectre v2 security enhancements, micro-operation cache algorithms, prefetcher advancements, and memory latency optimizations. Each micro-architecture item evolved over time, both as part of continuous yearly improvement, and in reaction to changing mobile workloads.