An analysis of SEU robustness of C-element structures implemented in bulk CMOS and SOI technologies
An analysis of SEU robustness of C-element structures implemented in bulk CMOS and SOI technologies
复制标题
对体 CMOS 和 SOI 技术中实现的 C 元件结构的 SEU 稳健性进行分析
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
A. Yakovlev
中科院分区：
文献类型：
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作者：
Z. A. Tarawneh;G. Russell;A. Yakovlev
市场对每单位面积更高性能和更大功能的需求一直是推动最小特征尺寸下降的力量。然而，解决这些市场需求的技术进步导致的几个意想不到的后果是电路对SEU的敏感性增加，以及确定定时参数的不确定性增加，这对实现定时收敛变得不利。通过采用异步设计风格，可以解决与时序收敛相关的一些问题以及因性能提高而导致的功耗增加。一个不仅被广泛使用而且是异步设计所特有的逻辑元件是Muller C元件，它可以在许多不同的配置中实现。鉴于增加敏感性的逻辑元件的影响，单粒子翻转装置的几何形状减少本文报告的各种C-元件配置的鲁棒性分析，在不同的技术，单粒子翻转的影响。已经观察到，在静态C元件配置中，对称C元件是最鲁棒的。
Market place demands for higher performance and greater functionality per unit area have been the force driving down minimum feature sizes. However, several unintended consequences resulting from the advances in technology to address these market place demands has been an increase in the susceptibility of the circuits to SEUs and a growing uncertainty in the determination of timing parameters which is becoming detrimental to achieving timing closure. Some of the issues related to timing closure and the associated increase in power dissipation resulting from the increase in performance can be addressed through the adoption of an asynchronous design style. A logic element which is not only widely used but also peculiar to asynchronous design is the Muller C-element, which can be realised in a number of different configurations. In view of the increased susceptibility of logic elements to the effects of SEUs as device geometries are reduced this paper reports on the analysis of the robustness of various C-element configurations implemented in different technologies, to the effects of SEUs. It has been observed that of the static C-element configurations the symmetric C-element is the most robust.