Design considerations for low-power, high-speed CMOS analog/digital converters
Design considerations for low-power, high-speed CMOS analog/digital converters
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低功耗、高速 CMOS 模拟/数字转换器的设计注意事项
DOI：
10.1109/lpe.1994.573208
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发表时间：
1994
期刊：
影响因子：
--
通讯作者：
Paul R. Gray
中科院分区：
文献类型：
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作者：
Thomas B. Cho;D. Cline;Cormac S.G. Conroy;Paul R. Gray
本文综述了在高速CMOSA/D转换器中实现低功耗的结构和电路设计。首先讨论了MOS采样器和量化器中可实现的功耗的基本限制。然后讨论了一个10位、20M采样/S流水线A/D转换器的设计，该A/D转换器采用1.2SPLMU/m工艺实现，在3.3V电源电压下实现了35 mW的全速功耗。
This paper reviews architectural and circuit design considerations for realization of low power dissipation in high-speed CMOS A/D converters. Basic limitations on achievable power dissipation in MOS samplers and quantizers is first discussed. Then a number of practical design aspects are illustrated with discussion of a 10-bit, 20-Msample/s pipeline A/D converter implemented in 1.2-/spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation on a 3.3 V power supply.