TIME INTERLEAVED CONVERTER ARRAYS
TIME INTERLEAVED CONVERTER ARRAYS
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DOI：
10.1109/jssc.1980.1051512
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发表时间：
1980-01-01
影响因子：
5.4
通讯作者：
HODGES, DA
中科院分区：
文献类型：
--
作者：
BLACK, WC;HODGES, DA
高速单片转换器通常使用闪存技术的一种变体，即2个/SUP n/比较器并行来获得快速的n位转换。虽然这种方法允许很高的转换器带宽，但它不是非常有效的面积，导致即使是中等分辨率的转换器也会产生较大的芯片尺寸。在这里提出的技术中，许多小但面积高效的转换器以时间交错的方式操作，以获得闪存电路的带宽，但面积要小得多。针对非理想阵列特性引起的噪声和失真进行了分析，并通过四路阵列测试芯片进行了验证。该芯片由4个时间交错的7位加权电容A/D转换器组成，采用10/SPLµ/m金属栅工艺。完整的7位线性度可保持高达2.5 MHz的转换速率，在降低线性度的情况下运行可持续到约4 MHz。描述了该芯片的设计，以及如果采用现代4-5/SPLµ/m工艺制造的预期特性。
High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described.