Time memory cell VLSI for the PHENIX drift chamber
Time memory cell VLSI for the PHENIX drift chamber
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用于 PHENIX 漂移室的时间存储单元 VLSI
DOI：
10.1109/nssmic.1997.672486
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发表时间：
1997
期刊：
影响因子：
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通讯作者：
T. Emura
中科院分区：
文献类型：
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作者：
Y. Arai;M. Ikeno;M. Sagara;T. Emura
高精度时间数字转换器 VLSI，TMC-PHX1，是为 PHENIX 漂移室开发的。该芯片包含 4 个 TDC 通道，具有两级数据缓冲和触发缓冲，这是非常高速率实验所必需的。除了固定数据大小读出外，该芯片还支持消零模式读出。该芯片记录上升沿和下降沿时序，最小时序计数分别为 0.83 ns/位和 1.66 ns/位。 1 级缓冲器的记录深度为 6.8 /spl mu/sec，读出 FIFO 的深度为 128 个字。高精度定时源自使用 PLL 稳定的非对称环形振荡器。该芯片的运行速度是 RHIC 束时钟的 4 倍（37.6 MHz），并采用 0.5 /spl mu/m CMOS 门阵列技术制造。
A high-precision Time-to-Digital-Converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and a trigger buffering which are necessary for very high rate experiments. In addition to the fixed data size readout, the chip also supports zero-suppression mode readout. The chip records both rising and falling edge timings, and has a least timing count of 0.83 ns/bit and 1.66 ns/bit respectively. A level 1 buffer has a recording depth of 6.8 /spl mu/sec and a readout FIFO has a depth of 128 words. High precision timing was derived from an asymmetric ring oscillator stabilized with a PLL. The chip runs at 4 times faster clock (37.6 MHz) of the RHIC bunch clock, and was fabricated with 0.5 /spl mu/m CMOS gate-array technology.