MOS Interface Defect Control in Ge/IIIV Gate Stacks
MOS Interface Defect Control in Ge/IIIV Gate Stacks
复制标题
Ge/IIIV 栅极堆栈中的 MOS 接口缺陷控制
DOI：
10.1149/08001.0109ecst
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发表时间：
2018
期刊：
影响因子：
--
通讯作者：
and M. Takenaka
中科院分区：
文献类型：
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作者：
S. Takagi;M. Ke;C. Y. Chang;C. Yokoyama;M. Yokoyama;T. Gotow;K. Nishi;and M. Takenaka
上级栅堆叠的形成和界面缺陷的物理来源的理解是实现高性能Ge/III-V CMOS的重要。本文提出了Ge/Ⅲ-Ⅴ MOS界面的几个关键问题。对于Ge栅堆叠，最困难的挑战之一是降低高密度的慢陷阱。为了明确慢陷阱的位置，陷阱的性质进行了研究，Al 2 O3/GeOx/Ge与不同的厚度。此外，纳入Y原子到GeOx界面层检查通过使用ALD Y2 O3用于降低慢陷阱密度。对于III-V MOS界面控制，研究了不同In含量的InGaAs在高k ALD前的表面处理对InGaAs MOS界面的影响。此外，我们还研究了ALD La_2O_3/InGaAs MOS界面对InGaAs MOSFET性能的影响。结果表明，La 2 O3/InGaAs MOSFET具有较低的亚阈值摆幅和较低的载流子俘获特性，但由于其较高的固定氧化层电荷密度，其迁移率低于Al 2 O3/InGaAs MOSFET。
Formation of superior gate stacks and understanding of physical origins of interface defects are important for realizing high performance Ge/III-V CMOS. In this paper, several critical issues on the Ge/III-V MOS interfaces are presented. For Ge gate stacks, one of the most difficult challenges is reduction in high density of slow traps. In order to clarify the location of slow traps, trapping properties are examined for Al2O3/GeOx/Ge with different thickness. Also, incorporation of Y atoms into GeOx interfacial layers is examined by using ALD Y2O3 for reducing the slow trap density. For III-V MOS interface control, the effects of surface treatment prior high k ALD on InGaAs MOS interfaces is studied for InGaAs with different In content. Also, we studied the impact of ALD La2O3/InGaAs MOS interfaces on the performance of InGaAs MOSFETs. It is found that La2O3/InGaAs MOSFETs exhibit lower sub-threshold swing and lower carrier trapping properties, while have lower mobility than Al2O3/InGaAs MOSFETs, because of higher fixed oxide charge density.