Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design

Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design
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异构 2.5D 小芯片封装协同设计的耦合提取和优化

DOI:
10.1145/3400302.3415718
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发表时间:
2020
期刊:
International Conference On Computer Aided Design (ICCAD
影响因子:
--
通讯作者:
Peng, Yarui
Peng, Yarui
中科院分区:
--
文献类型:
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作者:
Kabir, MD Arafat;Petranovic, Dusan;Peng, Yarui

文献摘要

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近年来,2.5D小芯片封装设计在异构技术的系统集成中越来越受欢迎。目前,不存在可以设计、分析和优化完整的异构 2.5D 系统的标准 CAD 流程。传统的逐芯片设计方法在提取和优化过程中不考虑任何封装层,并且如果不对标准 CAD 工具进行根本性改变,则精确的小芯片封装提取无法应用于异构设计。在本文中,我们介绍了高性能高密度 2.5D 系统的整体和上下文小芯片封装协同设计流程,使用标准 ASIC CAD 工具,IO 管道深度开销为零。我们的流程包括 2.5D 感知分区、小芯片封装协同规划、上下文提取、迭代优化以及整个 2.5D 系统的设计后分析和验证。我们使用布线和引脚规划策略来设计封装规划器,以最大限度地减少封装布线拥塞和时序开销。基于 ARM Cortex-M0 的微控制器系统被设计为基准。当在整体流程中考虑芯片封装相互作用时,与参考 2D 设计的性能差距减少了 62.5%。我们的上下文提取在同质系统上的接地和耦合电容误差仅为 0.71% 和 0.79%。此外,我们还实现了一个异构 2.5D 系统来展示我们新颖的上下文设计和优化方法。
In recent years, 2.5D chiplet package designs have gained popularity in system integration of heterogeneous technologies. Currently, there exists no standard CAD flow that can design, analyze, and optimize a complete heterogeneous 2.5D system. The traditional die-by-die design approach does not consider any package layers during extraction and optimization, and an accurate chiplet-package extraction can not be applied to heterogeneous designs without fundamental changes in standard CAD tools. In this paper, we present our Holistic and In-Context chiplet-package co-design flows for high-performance high-density 2.5D systems using standard ASIC CAD tools with zero overhead on IO pipeline depth. Our flow encompasses 2.5D-aware partitioning, chiplet-package co-planning, in-context extraction, iterative optimization, and post-design analysis and verification of the entire 2.5D system. We design our package planner with a routing and pin-planning strategy to minimize package routing congestion and timing overhead. An ARM Cortex-M0-based microcontroller system is designed as the benchmark. The performance gap to the reference 2D design reduces by 62.5% when chip-package interactions are taken into account in the holistic flow. Our in-context extraction achieves only 0.71% and 0.79% error on ground and coupling capacitance on a homogeneous system. Further, we implement a heterogeneous 2.5D system to demonstrate our novel in-context design and optimization methodology.