Suppression of stress induced open failures between via and Cu wide line by inserting Ti layer under Ta/TaN barrier
Suppression of stress induced open failures between via and Cu wide line by inserting Ti layer under Ta/TaN barrier
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通过在 Ta/TaN 势垒层下插入 Ti 层来抑制通孔和 Cu 宽线之间应力引起的开路故障
DOI：
10.1109/iedm.2002.1175946
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
Y. Hayashi
中科院分区：
文献类型：
--
作者：
M. Ueki;M. Hiroi;N. Ikarashi;T. Onodera;N. Furutake;M. Yoshiki;Y. Hayashi
我们验证了钛层插入应力诱导的空洞形成宽铜线路下形成的通孔空洞的效果。为了提高过孔与底层Cu之间的粘附性能，在Ta/TaN阻挡层下插入PVD-Ti。当插入标称30 nm厚的PVD-Ti层（在通孔底部的Ti厚度为约8 nm）时，故障被充分抑制而不降低电迁移电阻。此外，与传统的Ta/TaN势垒结构相比，通孔电阻降低了25%，而Cu金属的电阻率不受Ti插入的影响。
We verified the effect of Ti layer insertion on stress induced void formation in wide Cu lines where voids were formed under via. In order to improve adhesion property between via and underlying Cu, PVD-Ti was inserted under Ta/TaN barrier. When nominal 30 nm thick PVD-Ti layer was inserted (Ti thickness at via bottom was about 8 nm), the failure was sufficiently suppressed without degrading the electromigration resistance. In addition, the via resistance was reduced by 25% compared with conventional Ta/TaN barrier structure, while the Cu metal resistivity was unchanged by the Ti insertion.