Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs

Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs
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DOI:
10.1109/tvlsi.2022.3228850
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发表时间:
2023-03
影响因子:
2.8
通讯作者:
Arjun Chaudhuri;Sanmitra Banerjee;Jinwoo Kim;S. Lim;K. Chakrabarty
Arjun Chaudhuri;Sanmitra Banerjee;Jinwoo Kim;S. Lim;K. Chakrabarty
中科院分区:
工程技术2区
文献类型:
--
作者:
Arjun Chaudhuri;Sanmitra Banerjee;Jinwoo Kim;S. Lim;K. Chakrabarty

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整体3-D(M3D)IC中的纳米级中间层vias(ILV)已实现了逻辑和内存层的高密度垂直整合。但是,M3D层通过晶圆粘结的顺序组装容易出现未成熟制造过程和制造缺陷的变异性。通过使用内置的自我测试(BIST)对ILV的诊断,可以通过专门的测试和ILV诊断来减轻由于ILV断层引起的产量降解。先前的工作已经在M3D布局中定期进行ILV的常规1D放置进行了故障定位,在该布局中,假定短裤仅在单向ILV之间出现。但是,为了最大程度地减少M3D路由中的线长度,可以通过位置和路由工具不规则地放置ILV,并且短裤也可能发生在前进的ILV和下降的ILV之间。为了测试和定位在现实的ILV布局中的故障,我们提出了一个新的Bist框架,该框架已针对测试时间和PPA开销进行了优化。我们还提出了一种图形理论方法,用于表示ILV中潜在的故障位点,并进行电感断层分析以删除非关键位点。我们描述了一种将ILV最佳分配给士兵引脚的过程,并确定需要次测试成本最小化的轴心配置。 M3D基准的评估结果证明了所提出的框架的有效性。
Nanoscale interlayer vias (ILVs) in monolithic 3-D (M3D) ICs have enabled high-density vertical integration of logic and memory tiers. However, the sequential assembly of M3D tiers via wafer bonding is prone to variability in the immature fabrication process and manufacturing defects. The yield degradation due to ILV faults can be mitigated via dedicated test and diagnosis of ILVs using built-in self-test (BIST). Prior work has carried out fault localization for a regular 1-D placement of ILVs in the M3D layout where shorts are assumed to arise only between unidirectional ILVs. However, to minimize wirelength in M3D routing, ILVs may be irregularly placed by a place-and-route tool, and shorts can also occur between an up-going ILV and a down-going ILV. To test and localize faults in realistic ILV layouts, we present a new BIST framework that is optimized for test time and PPA overhead. We also present a graph-theoretic approach for representing potential fault sites in the ILVs and carry out inductive fault analysis to drop noncritical sites. We describe a procedure for optimally assigning ILVs to the BIST pins and determining the BIST configuration for test-cost minimization. Evaluation results for M3D benchmarks demonstrate the effectiveness of the proposed framework.