VLSI Hardware Architecture for Gaussian Process
VLSI Hardware Architecture for Gaussian Process
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DOI：
10.1109/ieeeconf51394.2020.9443272
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发表时间：
2020-11
期刊：
影响因子：
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通讯作者：
Chunhua Deng;Yongbin Gong;Feng Han;Siyu Liao;J. Yi;Bo Yuan
中科院分区：
文献类型：
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作者：
Chunhua Deng;Yongbin Gong;Feng Han;Siyu Liao;J. Yi;Bo Yuan
高斯过程（GP）是一种流行的机器学习技术，广泛应用于许多应用领域，特别是在机器人领域。然而，GP是非常计算密集型和耗时的推理阶段，从而带来了严峻的挑战，其大规模部署在实时应用。在本文中，我们提出了两个有效的硬件架构的GP加速器。一种架构针对一般GP推断，另一种架构针对逐渐观察数据点的场景进行了专门优化。评估结果表明，所提出的硬件加速器提供了显着的硬件性能比通用计算平台的改善。
Gaussian process (GP) is a popular machine learning technique that is widely used in many application domains, especially in robotics. However, GP is very computation intensive and time consuming during the inference phase, thereby bringing severe challenges for its large-scale deployment in real-time applications. In this paper, we propose two efficient hardware architecture for GP accelerator. One architecture targets for general GP inference, and the other architecture is specifically optimized for the scenario when the data point is gradually observed. Evaluation results show that the proposed hardware accelerator provides significant hardware performance improvement than the general-purpose computing platform.