On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit
On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit
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通过 65 nm CMOS 速度监控电路进行片上数字 Idn 和 Idp 测量
DOI：
10.1109/asscc.2008.4708813
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
H. Shinohara
中科院分区：
文献类型：
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作者：
H. Notani;M. Fujii;H. Suzuki;H. Makino;H. Shinohara
提出了一种片上数字I_<sub>ds</sub>测量方法。在所提出的方法中，I<sub>DS</sub>是从由三个环形振荡器与PN平衡，N-丰富，P-丰富的逆变器测量的两个值以数字方式导出的。第一个值是PN平衡反相器环的频率。第二个值是富N和富P反相器环之间的频率差。后数字处理分别导出NMOS I<sub>ds</sub>（I<sub>dn</sub>）和PMOS I<sub>ds</sub>（I<sub>dp</sub>）。监控电路采用65 nm CMOS工艺实现。分析了由实测频率计算出的第一I<sub>ds</sub>与直接测量的第二I<sub>ds</sub>之间的失配误差。<sub>Idn</sub>和<sub>Idp</sub>的失配误差的标准偏差分别为1.64%和1.09%。3sigma的裕度在5%以内，这是我们实际应用的目标公差。
An on-chip digital I<sub>ds</sub> measurement method is proposed in this report. In the proposed method, I<sub>ds</sub> is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS I<sub>ds</sub> (I<sub>dn</sub>) and PMOS I<sub>ds</sub> (I<sub>dp</sub>) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first I<sub>ds</sub> calculated from measured frequencies, and the second I<sub>ds</sub> directly measured for reference, was analyzed. The standard deviations of the mismatch error in I<sub>dn</sub> and I<sub>dp</sub> are 1.64% and 1.09%, respectively. The margin of 3sigma is within 5% which is our target tolerance for a practical application.