A low-power orthogonal current-reuse amplifier for parallel sensing applications
A low-power orthogonal current-reuse amplifier for parallel sensing applications
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DOI：
10.1109/esscirc.2010.5619839
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发表时间：
2010-11
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通讯作者：
Ben Johnson;David DeTomaso;A. Molnar
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文献类型：
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作者：
Ben Johnson;David DeTomaso;A. Molnar
我们展示了一个低噪声CMOS放大器阵列，使用正交偏置电流重用，以改善基本的噪声功率权衡。所提出的架构使用堆叠在四个放大器的输入差分对之间共享偏置电流。通过使用每个差分对的输出漏极电流作为下一级的尾电流，我们节省了偏置电流。通过适当排列堆叠差分对，我们生成16个输出电流，这些电流以线性独立（正交）方式对原始输入进行编码。然后，这些输出在低得多的功率输出级中重新组合，以重建输入的放大版本。我们的设计采用标准130 nm CMOS，噪声效率因子（NEF）为2.7，接近差分放大器的最低水平。然而，在NEF计算中分摊跨4个并联放大器路径的偏置电流产生1.54的有效NEF。参考输入的噪声范围为14.5 ßVrms至17.4 /iVrm。在426 kHz至530.2 kHz的带宽上，堆叠中的放大器之间的串扰最小，而每条路径的总功耗为19.6 μ W或4.9 μ W。正交偏置避免了堆叠放大器路径之间的串扰，提供37 dB或更好的隔离。
We demonstrate a low-noise CMOS amplifier array using orthogonal bias current-reuse to improve fundamental noise-power trade-offs. The architecture presented uses stacking to share bias current among the input differential pairs of four amplifiers. By using the output drain currents of each differential pair as tail currents for the next stage, we save bias current. By arranging the stacked differential pairs appropriately, we generate 16 output currents that encode the original inputs in a linearly independent (orthogonal) fashion. These outputs are then recombined in much lower power output stages to reconstruct amplified versions of the inputs. Our design was built in standard 130nm CMOS and has a noise efficiency factor (NEF) of 2.7, close to the lowest published for a differential amplifier. However, amortizing bias current across the 4 parallel amplifier paths in the NEF calculation yields an effective NEF of 1.54. The input-referred noise ranges from 14.5 ßVrms to 17.4 /iVrm. between amplifiers in the stack over bandwidths of 426 kHz to 530.2 kHz while consuming a total power of 19.6 μ-W, or 4.9 μ\¥ per path. Orthogonal biasing avoids cross-talk between stacked amplifier paths, providing isolation of 37 dB or better.