A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications
A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications
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DOI：
10.1007/s11432-013-4949-8
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发表时间：
2014-03
期刊：
影响因子：
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通讯作者：
Zhongyuan Hou;Fan Yang;Junhua Liu;Xing Zhang
中科院分区：
文献类型：
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作者：
Zhongyuan Hou;Fan Yang;Junhua Liu;Xing Zhang
本文提出了一种低功耗、低成本的1.0625-3.125 Gb/s串行收发器，适用于光纤通道（FC）、快速外围组件互连（PCIe）和RapidIO应用。为了通过单一低功耗和低成本设计支持多种标准，本文介绍的收发器采用宽摆幅范围源串联端接（SST）发射器（TX）、无源接收器（RX）均衡器、双环锁相环（PLL）以及混合信号时钟和数据恢复（CDR）单元。建议SST发射机还实现了一个3位2抽头去加重滤波器，补偿高达6 dB的发射机，和一个无源均衡器，在接收机中实现4 dB的传输。采用带片内稳压器的双环路PLL，为TX和CDR的基准产生低抖动时钟。提出了一种具有相位差（PI）的CDR，该CDR具有混合信号结构以恢复RX上的时钟，并且它可以容忍高达2000 ppm的频率偏移。该收发器采用130 nm数字CMOS工艺制造，占地面积为0.8 mm 2。当电源电压为1.2 V和3.3 V时，收发器在3.125 Gb/s时补偿10 dB的总损耗时，功耗为78 mW。
A power-efficient and low-cost 1.0625–3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel (FC), Peripheral Component Interconnect Express (PCIe), and RapidIO applications. To support multiple standards with a single low power and low cost design, the transceiver presented here uses a wide swing range source-series-terminated (SST) transmitter (TX), a passive receiver (RX) equalizer, a dual-loop phase locked loop (PLL) and a mixed signal clock and data recovery (CDR) unit. The proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter, and a passive equalizer that achieves 4 dB transmission in the receiver. The dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR’s reference. A CDR with a phase interpolator (PI) is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 ppm. The transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 mm2. With supply voltages of 1.2 V and 3.3 V, the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at 3.125 Gb/s.