Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices
Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices
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DOI：
10.1109/dsn.2019.00017
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发表时间：
2019-06
期刊：
影响因子：
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通讯作者：
Minesh Patel;Jeremie S. Kim;Hasan Hassan;O. Mutlu
中科院分区：
文献类型：
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作者：
Minesh Patel;Jeremie S. Kim;Hasan Hassan;O. Mutlu
DRAM错误的实验表征是了解DRAM行为的一项强大技术，并为提高整体系统性能、能效和可靠性提供了有价值的见解。不幸的是，最近的DRAM技术扩展问题迫使制造商采用片上纠错码(ECC)，这对DRAM错误表征研究构成了重大挑战，因为它使用未记录的、专有的和不透明的纠错硬件来混淆原始错误分布。正如我们在这项工作中所展示的，在具有片上ECC的器件中观察到的误差不再遵循预期的、经过充分研究的分布(例如，对数正态保持时间)，而是取决于所使用的特定ECC方案。
Experimental characterization of DRAM errors is a powerful technique for understanding DRAM behavior and provides valuable insights for improving overall system performance, energy efficiency, and reliability. Unfortunately, recent DRAM technology scaling issues are forcing manufacturers to adopt on-die error-correction codes (ECC), which pose a significant challenge for DRAM error characterization studies by obfuscating raw error distributions using undocumented, proprietary, and opaque error-correction hardware. As we show in this work, errors observed in devices with on-die ECC no longer follow expected, well-studied distributions (e.g., lognormal retention times) but rather depend on the particular ECC scheme used.