Droop mitigating last level cache architecture for STTRAM
Droop mitigating last level cache architecture for STTRAM
复制标题
STTRAM 的下降缓解末级缓存架构
DOI：
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发表时间：
2017
期刊：
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通讯作者：
Swaroop Ghosh
中科院分区：
文献类型：
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作者：
Radha Krishna Aluru;Swaroop Ghosh
自旋转移矩随机存取存储器（STTRAM）是新兴的非易失性存储器（NVM）技术之一，尤其优选用于末级高速缓存（LLC）。切换磁化所需的电流量很高（每比特100 μ A）。对于全高速缓存行（512位）写入，该极高电流导致常规高速缓存架构中的电压下降。由于这种下降，写操作失败，尤其是当访问该高速缓存的最远存储体时。在本文中，我们提出了一种新的缓存架构，以减轻这个问题的下垂，使写操作成功。代替在单个存储体中连续地写入整个高速缓存行（512位），所提出的架构在跨该高速缓存的多个物理上分离的位置中写入64位。得到的仿真结果（电路和微架构）比较我们提出的架构对传统的被发现是1.96%（IPC）和5.21%（能源）。
Spin-Transfer Torque Random Access Memory (STTRAM) is one of the emerging Non-Volatile Memory (NVM) technologies especially preferred for the Last Level Cache (LLC). The amount of current needed to switch the magnetization is high (∼100ßA per bit). For a full cache line (512-bit) write, this extremely high current results in a voltage droop in the conventional cache architecture. Due to this droop, the write operation fails especially, when the farthest bank of the cache is accessed. In this paper, we propose a new cache architecture to mitigate this problem of droop and make the write operation successful. Instead of continuously writing the entire cache line (512-bit) in a single bank, the proposed architecture writes 64-bits in multiple physically separated locations across the cache. The simulation results obtained (both circuit and micro-architectural) comparing our proposed architecture against the conventional are found to be 1.96% (IPC) and 5.21% (energy).