High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm
High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm
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DOI：
10.1109/tvlsi.2011.2147811
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发表时间：
2012-07
影响因子：
2.8
通讯作者：
Yang Sun;Joseph R. Cavallaro
中科院分区：
文献类型：
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作者：
Yang Sun;Joseph R. Cavallaro
本文提出了一种新的路径保持网格搜索（PPTS）算法及其用于软输出多输入多输出（MIMO）检测的高速VLSI结构。我们用无约束网格表示MIMO信号的搜索空间，其中网格的阶段k中的每个节点映射到由天线k发送的可能的复值符号。基于网格模型，我们将软输出MIMO检测问题转化为一个多最短路径问题的约束，每个网格节点必须覆盖在这组路径。PPTS检测器保证具有在每个天线上发送的每个可能符号的软信息，使得可以更准确地形成每个发送数据比特的对数似然比（LLR）。仿真结果表明，PPTS算法能够以较低的搜索复杂度获得接近最优的误码性能。PPTS算法是一种硬件友好的数据并行算法，因为搜索操作均匀分布在多个网格节点之间进行并行处理。作为一个案例研究，我们已经设计和综合了一个完全并行的收缩阵列检测器和两个折叠检测器的4 × 4 16-QAM系统使用1.08 V TSMC 65-nm CMOS工艺。在1.18 mm 2的核心面积下，折叠探测器可以实现2.1 Gbps的吞吐量。该全并行系统阵列探测器的核心面积为3.19 mm 2，吞吐量可达6.4 Gbps。
In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage k of the trellis maps to a possible complex-valued symbol transmitted by antenna k. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4 × 4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm2 core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps.