A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency
A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency
复制标题
DOI：
--
复制
发表时间：
2013-06
期刊：
影响因子：
--
通讯作者：
Chien-Fu Chen;Ting-Hao Chang;Lai-Fu Chen;Meng-Fan Chang;H. Yamauchi
中科院分区：
文献类型：
--
作者：
Chien-Fu Chen;Ting-Hao Chang;Lai-Fu Chen;Meng-Fan Chang;H. Yamauchi
这项工作提出了一种具有双数据感知写辅助（D2 AW）和负读WL（NRWL）方案的8 T单元，以增加品质因数（FOM）：[单元稳定性（CS）* 周期频率（f）]/[单元面积（A）* 最小VDD（VDD min）]。基于列的D2 AW首次提供了行/列半选（HS）-CS裕量和写裕量（WM）之间的权衡解决方案，这要归功于以下双重数据感知控制：1）单元VSS（DA-CVSS）和2）写操作（DA-WWL）。NRWL扩大了RBL电压摆幅（VRBLs），同时加速了BL发展时间（TBLS）。在VDD= 210 mV/300 mV时，已制作的65 nm 128行16 Kb D2 AW 8 T SRAM的工作频率为7.3MHz/48 MHz。所得到的“CS*f/（A*VDDmin）”比其他低VDDmin SRAM单元的高14+x。
This work proposes an 8T cell with dual data-aware write-assist (D2AW) and negative read-WL (NRWL) schemes to increase the figure of merit (FOM): [cell stability (CS)*cycle frequency (f)]/[cell area (A)*minimum VDD (VDDmin)]. The column-based D2AW provides, for the first time, the solution to the trade-off between the row/column half-select (HS)-CS margins and the write margin (WM) thanks to the dual data-aware controls of: 1) cell-VSS (DA-CVSS) and 2) write-wordline (DA-WWL). NRWL expands the RBL voltage swing (VRBLS), while accelerating BL developing time (TBLS). A fabricated 65nm 128-row 16Kb D2AW8T SRAM achieved 7.3MHz/48MHz at VDD=210mV/300mV. The resulting “CS*f/(A*VDDmin)” is 14+x higher than that of other low-VDDmin SRAM cells.