A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy
A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy
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DOI：
10.23919/date.2019.8714868
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发表时间：
2019-03
期刊：
影响因子：
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通讯作者：
M. S. Ansari;B. Cockburn;Jie Han
中科院分区：
文献类型：
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作者：
M. S. Ansari;B. Cockburn;Jie Han
对数乘法器取操作数的以2为底的对数，仅使用移位和加法运算执行乘法。由于计算对数通常是一个近似过程，因此在此类设计中不可避免地会损失一些精度。然而，面积、延迟和功耗可以以精度损失为代价显著改善。本文提出了一种新的方法来近似log 2N，不同于现有的方法，四舍五入N到它的最近的2的幂，而不是2的最高幂小于或等于N。然后利用这种近似技术设计了两个改进的16×16对数乘法器，分别使用精确加法器和近似加法器（ILM-EA和ILM-AA）。这些乘法器实现了高达24.42%和9.82%的面积和功耗延迟产品，分别节省相比，在文献中的最先进的设计具有类似的精度。在联合图像专家组（JPEG）的图像压缩算法和其他近似对数乘法器的优势进行评估所提出的设计。
Logarithmic multipliers take the base-2 logarithm of the operands and perform multiplication by only using shift and addition operations. Since computing the logarithm is often an approximate process, some accuracy loss is inevitable in such designs. However, the area, latency, and power consumption can be significantly improved at the cost of accuracy loss. This paper presents a novel method to approximate log2N that, unlike the existing approaches, rounds N to its nearest power of two instead of the highest power of two smaller than or equal to N. This approximation technique is then used to design two improved 16×16 logarithmic multipliers that use exact and approximate adders (ILM-EA and ILM-AA, respectively). These multipliers achieve up to 24.42% and 9.82% savings in area and power-delay product, respectively, compared to the state-of-the-art design in the literature with similar accuracy. The proposed designs are evaluated in the Joint Photographic Experts Group (JPEG) image compression algorithm and their advantages over other approximate logarithmic multipliers are shown.