Towards a Design Flow for Reversible Logic
Towards a Design Flow for Reversible Logic
复制标题
可逆逻辑的设计流程
DOI：
10.1007/978-90-481-9579-4
复制
发表时间：
2010
影响因子：
--
通讯作者：
R. Drechsler
中科院分区：
文献类型：
--
作者：
R. Wille;R. Drechsler
1.引言。2.预赛。2.1.背景资料。2.2.决策图。2.3.满足性求解器。3.可逆逻辑的综合。3.1.当前合成步骤。3.2.基于BDD的综合。3.3.SyReC：一种可逆的硬件语言。3.4.总结和未来的工作。4.可逆逻辑的精确综合。4.1.主流道。4.2.基于SAT的精确合成。4.3.改进了精确合成。4.4.总结和未来的工作。5.不可逆函数的嵌入。5.1.嵌入问题。5.2.别管任务了。5.3.输出排列法综合。5.4.总结和未来的工作。6.优化。6.1.增加线路以降低电路成本。6.2.减少回路线数。6.3.线性近邻体系结构的电路优化。6.4.总结和未来的工作。7.正式验证和调试。7.1.等价性检查。7.2.自动调试和修复。7.3.总结和未来的工作。8.总结与结论。参考资料。索引。
1. Introduction. 2. Preliminaries. 2.1. Background. 2.2. Decision Diagrams. 2.3. Satisfiability Solvers. 3. Synthesis of Reversible Logic. 3.1. Current Synthesis Steps . 3.2. BDD-based Synthesis. 3.3. SyReC: A Reversible Hardware Language. 3.4. Summary and Future Work. 4. Exact Synthesis of Reversible Logic. 4.1. Main Flow. 4.2. SAT-based Exact Synthesis. 4.3. Improved Exact Synthesis. 4.4. Summary and Future Work. 5. Embedding of Irreversible Functions. 5.1. Embedding Problem. 5.2. Don't Care Assignment. 5.3. Synthesis with Output Permutation. 5.4. Summary and Future Work. 6. Optimization. 6.1. Adding Lines to Reduce Circuit Cost. 6.2. Reducing the Number of Circuit Lines. 6.3. Optimizing Circuits for Linear Nearest Neighbor Architectures. 6.4. Summary and Future Work. 7. Formal Veri?cation and Debugging. 7.1. Equivalence Checking. 7.2. Automated Debugging and Fixing. 7.3. Summary and Future Work. 8. Summary and Conclusions. References. Index.