Realization of multiple-output functions by reconfigurable cascades
Realization of multiple-output functions by reconfigurable cascades
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通过可重构级联实现多输出功能
DOI：
10.1109/iccd.2001.955056
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
M. Matsuura
中科院分区：
文献类型：
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作者：
Y. Iguchi;Tsutomu Sasao;M. Matsuura
本文提出了一种用RAM和序列器实现多路输出逻辑功能的方法。首先，多输出函数由非零编码特征函数（ECFN）表示。然后，它由级联的查找表（LUT）表示。最后用RAM和时序器对级联进行了模拟。基准函数的多输出函数通过LUT的级联实现，并且示出了LUT的数量和级联的级别。提出了一种并行计算的输出划分方法。利用RAM和FPGA开发了一个原型系统。该实现使用时域复用，并且对于输出引脚数量有限的情况很有用。
A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). Finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for benchmark functions are realized by cascades of LUTs, and the number of LUTs and levels of cascades are shown. A partition method of outputs for parallel evaluation is also presented. A prototype has been developed by using RAM and FPGA. This realization uses time domain multiplexing, and is useful for the case where the number of output pins is limited.