Device and technology optimizations for low power design in deep sub-micron regime
Device and technology optimizations for low power design in deep sub-micron regime
复制标题
深亚微米领域低功耗设计的器件和技术优化
DOI：
10.1145/263272.263363
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发表时间：
1997
期刊：
影响因子：
--
通讯作者：
C. Hu
中科院分区：
文献类型：
--
作者：
Kai Chen;C. Hu
本报告基于 CMOS 缩放和栅极延迟模型的最新分析和实验研究，重新审视了驱动电流 I/sub dsat/、传播延迟 t/sub pd/ 和开关能量 E 等基本设计量，并研究了深亚微米范围内的器件优化问题。提取了经验 I/sub dsat/ 方程和器件优化指南，包括栅极氧化物、沟道长度和电源缩放以及互连负载。
This report, based on the most recent analytical and experimental studies of CMOS scaling and gate delay models, reexamines the fundamental design quantities such as driving current, I/sub dsat/, propagation delay, t/sub pd/, and switching energy, E, and investigates device optimization issues in deep sub-micron regime. Empirical I/sub dsat/ equations and device optimization guidelines with gate oxide, channel length and power supply scaling as well as interconnect loading are extracted.