FLexiTASK: A Flexible FPGA Overlay for Efficient Multitasking
FLexiTASK: A Flexible FPGA Overlay for Efficient Multitasking
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FLexiTASK：用于高效多任务处理的灵活 FPGA 叠加
DOI：
10.1145/3194554.3194644
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
C. Bobda
中科院分区：
文献类型：
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作者：
Joel Mandebi Mbongue;Danielle Tchuinkou Kwadjo;C. Bobda
在高性能计算中采用 FPGA 的主要障碍之一是其可编程性。它需要硬件设计技能和较长的编译时间。叠加已被提议作为抽象 FPGA 资源的一种方式。不幸的是，大多数时候，它们用于连接计算核心的拓扑对任务的放置位置以及它们的通信方式施加了限制。在本文中，我们提出了一种旨在提高效率和灵活性的覆盖架构。它具有新颖的片上网络 (NoC) 基础设施，可灵活且不受限制地放置硬件任务。所提出的架构允许任务以低延迟进行通信，并简化运行时结构上所需区域的重新配置。在 Altera Cyclone V FPGA 上对所提出的架构进行原型设计后，最高频率已达到 282 MHz，并且与本机执行相比，在某些应用中观察到加速范围为 4 倍到 195 倍。
One of the major obstacles to the adoption of FPGAs in high-performance computing is their programmability. It requires hardware design skills and long compilation times. Overlays have been proposed as a way to abstract FPGA resources. Unfortunately, most of the time, the topologies they use to connect computing cores impose restrictions on where tasks are placed and how they communicate. In this paper, we propose an overlay architecture designed for efficiency and flexibility. It features a novel Network-on-Chip (NoC) infrastructure making flexible, with no limitation, the placement of hardware tasks. The presented architecture allows tasks to communicate with a low latency and eases the reconfiguration of desired areas on the fabric at runtime. After prototyping the proposed architecture on an Altera Cyclone V FPGA, a maximum frequency of 282 MHz has been reached and a speedup ranging from 4x to 195x has been observed in some applications compared to the native execution.