Toggle MUX: How X-optimism can lead to malicious hardware
Toggle MUX: How X-optimism can lead to malicious hardware
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DOI：
10.1145/3061639.3062328
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发表时间：
2017-06
期刊：
影响因子：
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通讯作者：
Christian Krieg;C. Wolf;A. Jantsch;T. Zseby
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文献类型：
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作者：
Christian Krieg;C. Wolf;A. Jantsch;T. Zseby
为了突出对硬件安全的潜在威胁，我们提出了一种方法来获得一个触发信号的行为的Verilog仿真模型的现场可编程门阵列（FPGA）原语的行为X乐观。我们展示了我们的方法与一个例子触发器，使用Xilinx 7系列FPGA实现。实验结果表明，可以很容易地创建一个触发信号，在模拟（合成前和合成后）中为“0”，在硬件中为“1”。我们表明，这种触发器既不能检测到正式的等价性检查，也不是最近的木马检测技术。作为一种对策，我们建议仔细重新考虑在FPGA仿真模型中使用X-乐观。
To highlight a potential threat to hardware security, we propose a methodology to derive a trigger signal from the behavior of Verilog simulation models of field-programmable gate array (FPGA) primitives that behave X-optimistic. We demonstrate our methodology with an example trigger that is implemented using Xilinx 7 Series FPGAs. Experimental results show that it is easily possible to create a trigger signal that is ‘0’ in simulation (pre- and post-synthesis), and ‘1’ in hardware. We show that this kind of trigger is neither detectable by formal equivalence checks, nor by recent Trojan detection techniques. As a countermeasure, we propose to carefully reconsider the utilization of X-optimism in FPGA simulation models.