Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis
Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis
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通过闭式分析了解亚阈值 CMOS 逻辑的 DC 行为
DOI：
10.1109/tcsi.2009.2034233
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
M. Alioto
中科院分区：
文献类型：
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作者：
M. Alioto
本文在文献中首次以封闭形式分析了亚阈值CMOS逻辑的直流行为。为此，首先建立了亚阈值MOS晶体管的大信号和小信号简化模型。在用这些等效模型替换晶体管后，分析了CMOS逻辑门的主要直流参数。特别是，详细分析了超低电压运行引起的直流特性形状的变化，解析地评估了逻辑摆幅的退化、过渡区的对称性和陡度以及单位增益点位置的变化。由此得到的表达式允许深入了解直流行为对设计和器件参数的基本依赖。噪声裕度通过一个非常简单的表达式进行显式评估和建模。有趣的是，分析表明，噪声裕度偏离理想的半摆动值的程度与pn比的对数成线性关系。分析允许评估确保正确操作的最小电源电压(即正噪声容限)。以前提出的估算最小电压的经验法则在理论上也是合理的。此外，从设计角度分析了PMOS/NMOS不平衡对直流特性的影响。还介绍了对工艺/电压/温度变化的影响的考虑。结果通过在65 nm CMOS工艺中的广泛模拟得到验证。
In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependence of DC behavior on design and device parameters. The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the pn -ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of pMOS/nMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology.