Architecture of RETE Network Hardware Accelerator for Real-Time Context-Aware System
Architecture of RETE Network Hardware Accelerator for Real-Time Context-Aware System
复制标题
用于实时上下文感知系统的 RETE 网络硬件加速器架构
DOI：
10.1007/11892960_49
复制
发表时间：
2006
影响因子：
2.1
通讯作者：
J. Jeon
中科院分区：
文献类型：
--
作者：
Seung Wook Lee;Jong Tae Kim;Hongmoon Wang;Dae Jin Bae;Keon;Jee;J. Jeon
上下文感知系统，如智能家庭护理系统或移动通信设备，可以感知通道环境，需要推理能力与众多规则来管理当前上下文。基于规则系统的推理技术可以用于这些众多规则的有效推理方法。RETE算法已被用于基于规则的系统中推理规则的匹配。然而，RETE算法的特点使其在冯·诺依曼计算机系统中表现不佳。在本文中，我们提出了一种新的RETE网络硬件加速器架构，提供了高效的推理处理性能。利用并行RETE网络硬件架构，该加速器可以克服冯·诺依曼计算机系统的架构限制。
Context-aware systems, such as intelligent home-care systems or mobile communication devices that are aware of the channel environment, need reasoning ability with numerous rules to manage the current context. Reasoning techniques based on rule-based systems can be used for the efficient reasoning method of these numerous rules. The RETE algorithm has been used for the matching of reasoning rules in rule-based systems. However, the characteristics of the RETE algorithm cause it to have poor performance in Von Neumann computer systems. In this paper, we propose a novel architecture for the RETE network hardware accelerator, which provides efficient reasoning processing performance. Using the parallel RETE network hardware architecture, this accelerator can overcome the architectural constraints imposed by Von Neumann computer systems.