WaLo: Security Primitive Generator for RT-Level Logic Locking and Watermarking
WaLo: Security Primitive Generator for RT-Level Logic Locking and Watermarking
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DOI：
10.1109/asianhost51057.2020.9358262
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发表时间：
2020-12
期刊：
影响因子：
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通讯作者：
Jun Kuai;Jiaji He;Haocheng Ma;Yiqiang Zhao;Yumin Hou;Yier Jin
中科院分区：
文献类型：
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作者：
Jun Kuai;Jiaji He;Haocheng Ma;Yiqiang Zhao;Yumin Hou;Yier Jin
Various hardware security solutions have been developed recently to help counter hardware level attacks such as hardware Trojan, integrated circuit (IC) counterfeiting and intellectual property (IP) clone/piracy. However, existing solutions often provide specific types of protections. While these solutions achieve great success in preventing even advanced hardware attacks, the compatibility of among these hardware security methods are rarely discussed. The inconsistency hampers with the development of a comprehensive solution for hardware IC and IP from various attacks. In this paper, we develop a security primitive generator to help solve the compatibility issue among different protection techniques. Specifically, we focus on two modern IC/IP protection methods, logic locking and watermarking. A combined locking and watermarking technique is developed based on enhanced finite state machines (FSMs). The security primitive generator will take user-specified constraints and automatically generate an FSM module to perform both logic locking and watermarking. The generated FSM can be integrated into any designs for protection. Our experimental results show that the generator can facilitate circuit protection and provide the flexibility for users to achieve a better tradeoff between security levels and design overheads.
