Area-Efficient Reconfigurable Architecture for Media Processing
Area-Efficient Reconfigurable Architecture for Media Processing
复制标题
用于媒体处理的区域高效可重构架构
DOI：
10.1093/ietfec/e91-a.12.3651
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
I. Shirakawa
中科院分区：
文献类型：
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作者：
Y. Mitsuyama;Kazuma Takahashi;Rintaro Imai;M. Hashimoto;T. Onoye;I. Shirakawa
摘要提出了一种专用于媒体处理的面积有效的动态可重构架构。为了实现可以在消费者应用中使用的紧凑但高性能的设备，可重新配置的架构独特地执行媒体处理所需的8位操作，而细粒度的操作在主机处理器的协作下执行。异构可重构阵列由四种类型的单元组成，通过将应用领域集中在媒体处理上来减少配置数据的大小。实现结果表明，该可重构结构可以实现1.1 × 1. 4m m2，采用90 nm CMOS工艺。
SUMMARY An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.1 × 1. 4m m2 in a 90 nm CMOS technology.