Design of a predictive filter cache for energy savings in high performance processor architectures
Design of a predictive filter cache for energy savings in high performance processor architectures
复制标题
设计预测滤波器缓存以实现高性能处理器架构中的节能
DOI：
10.1109/iccd.2001.955005
复制
发表时间：
2001
期刊：
影响因子：
--
通讯作者：
A. Nicolau
中科院分区：
文献类型：
--
作者：
Weiyu Tang;Rajesh K. Gupta;A. Nicolau
过滤器缓存已经被提出作为一种节能的建筑特征。过滤器高速缓存被放置在CPU和指令高速缓存(I-高速缓存)之间以提供指令流。通过访问较小的缓存实现节能。然而，当在过滤器高速缓存中找不到指令时，存在性能损失。过滤器高速缓存节省的大部分能源是由于在小循环中暂时重复使用指令。我们检查后续提取地址以动态预测下一个提取地址是否在过滤器高速缓存中。在预测未命中的情况下，我们通过直接访问I-CACHE来减少未命中惩罚。实验结果表明，与传统的过滤缓存相比，我们的下一次获取预测降低了91%以上的性能损失，并具有更高的能效。我们的过滤器缓存设计可以实现平均31%的I-缓存节能，同时性能下降约1%。
Filter cache has been proposed as an energy saving architectural feature. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruction stream. Energy savings result from accesses to a small cache. There is however loss of performance when instructions are not found in the filter cache. The majority of the energy savings from the filter cache are due to the temporal reuse of instructions in small loops. We examine subsequent fetch addresses to predict whether the next fetch address is in the filter cache dynamically. In case a miss is predicted, we reduce miss penalty by accessing the I-cache directly. Experimental results show that our next fetch prediction reduces performance penalty by more than 91% and is more energy efficient than a conventional filter cache. Average I-cache energy savings of 31 % can be achieved by our filter cache design with around 1 % performance degradation.