An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips
An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips
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用于部分可重构片上系统的集成开发工具集和实现方法
DOI：
10.1109/asap.2011.6043272
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
A. Gordon
中科院分区：
文献类型：
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作者：
Abelardo Jara;A. Gordon
部分重新配置（PR）通过提供额外的益处（例如与非PR SoC相比减小的面积和增加的功能）来增强传统的基于FPGA的片上系统（SoC）。然而，由于利用这些额外的好处需要特定的设计师专业知识和增加的开发时间，PR尚未获得广泛的使用。在本文中，我们提出了一个集成的开发工具集，自动化的FPGA器件上的PR SoC的实施，并利用此工具在快速设计空间探索的案例研究。
Partial reconfiguration (PR) enhances traditional FPGA-based system-on-chips (SoCs) by providing additional benefits such as reduced area and increased functionality as compared to non-PR SoCs. However, since leveraging these additional benefits requires specific designer expertise and increased development time, PR has not yet gained widespread usage. In this paper, we present an integrated development toolset that automates the implementation of PR SoCs on FPGA devices and leverage this tool in a rapid design space exploration case study.