A Tuning Method of Programmable Delay Element with Two Values for Yield Improvement
A Tuning Method of Programmable Delay Element with Two Values for Yield Improvement
复制标题
一种提高良率的二值可编程延迟元件调谐方法
DOI：
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发表时间：
2013
期刊：
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通讯作者：
Y. Kohira
中科院分区：
文献类型：
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作者：
H. Mashiko;Y. Kohira
由于大规模集成电路工艺技术的进步和制造后布线和门延迟的变化增加，时序违规导致大规模集成电路芯片的产量显着下降。为了恢复时序违规，在制造之前将称为PDE的可编程延迟元件插入时钟树中，并在制造后调整其延迟。在本文中，我们使用两个延迟值的偏微分方程，并提出了一种延迟调整方法的偏微分方程，以提高成品率，减少测试的数量。此外，我们评估所提出的方法在商业CAD工具上获得的电路。实验结果表明该方法是有效的。
Due to progressing the process technology in LSI and increasing variations of wire and gate delays after fabrication, timing violations cause significant reduction in the yield of LSI chips. To recover the timing violations, programmable delay elements called PDEs are inserted into the clock tree before fabrication and their delays are tuned after fabrication. In this paper, we use PDEs with two delay values and propose a delay tuning method of the PDEs to improve the yield and to reduce the number of tests. Moreover, we evaluate the circuits obtained by the proposed method on commercial CAD tools. Experimental results show that the proposed method is effective.