Challenges, developments and applications of silicon deep reactive ion etching
Challenges, developments and applications of silicon deep reactive ion etching
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DOI：
10.1016/s0167-9317(03)00089-3
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发表时间：
2003-06-01
影响因子：
2.3
通讯作者：
Urban, A
中科院分区：
文献类型：
--
作者：
Laermer, F;Urban, A
高刻蚀速度，良好的均匀性和轮廓控制，高宽高比能力和可靠的介电界面陷波抑制是硅驱动加工工业应用的关键要求。在感应等离子体源的高功率电平（3kw）下，结合空间离子识别和准直，用于平衡RF驱动的优化硬件可产生超过10 μ m/min的蚀刻速率，具有出色的轮廓和速率分布均匀性（在6英寸以上+/-1.5%）。晶圆片，20%开放面积)。通过参数自适应策略，从重钝化配方开始，在工艺过程中稳步降低钝化负荷，实现了高宽高比沟槽的蚀刻和CD损耗的降低。比较了不同的衬底脉冲偏置方案对介电界面切迹抑制的潜力以及由此产生的对轮廓和工艺窗口的副作用。(C) 2003 Elsevier Science B.V.版权所有
High etching speed, good uniformity and profile control, high aspect ratio capabilities and reliable notching suppression at dielectric interfaces are key requirements in the industrial application of silicon DRIE processing. An optimized hardware for balanced RF drive at high power levels (3 kW) of the inductive plasma source in combination with spatial ion discrimination and collimation yields etch-rates in excess of 10 mum/min with excellent uniformity of profile and rate distribution (+/-1.5% over 6 in. wafers, 20% open area). Etching of high aspect-ratio trenches and reduction of CD loss is achieved by parameter adaptation strategies, starting from a passivation-heavy recipe and reducing the passivation load steadily during process progress. Different substrate pulsed-biasing schemes are compared with respect to their potential to suppression of notching at the dielectric interface and resulting side-effects on profile and process window. (C) 2003 Elsevier Science B.V. All rights reserved.