Lateral DMOS design for ESD robustness
Lateral DMOS design for ESD robustness
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DOI：
10.1109/iedm.1997.650403
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发表时间：
1997-12
期刊：
影响因子：
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通讯作者：
C. Duvvury;Fernando D. Carvajal;C. Jones;David D. Briggs
中科院分区：
文献类型：
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作者：
C. Duvvury;Fernando D. Carvajal;C. Jones;David D. Briggs
提出了一种有效的横向DMOS（LDMOS）功率管ESD保护设计。使用ESD条件下的LDMOS晶体管的特性与各种栅极和漏极钳位，建立了最小功耗的设计。结果表明，对于ESD制度的脉冲的沟道热效应是最小的，最佳的ESD水平可以通过驱动器件到最大可能的MOS导通。在此基础上，导出了有效ESD设计的经验公式。
This paper presents the design of efficient ESD protection in lateral DMOS (LDMOS) power transistor. Using characterization of the LDMOS transistor under ESD conditions with various gate and drain clamps, the design for minimum power dissipation is established. The results show that for ESD regime of pulses the channel heating effects are minimum and that optimum ESD level can be achieved by driving the device into maximum possible MOS conduction. Based on these results, an empirical formula for effective ESD design is derived.