An FPGA Accelerator for PatchMatch Multi-View Stereo Using OpenCL
An FPGA Accelerator for PatchMatch Multi-View Stereo Using OpenCL
复制标题
使用 OpenCL 实现 PatchMatch 多视图立体的 FPGA 加速器
DOI：
10.1007/s11554-017-0745-9
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发表时间：
2018
影响因子：
3
通讯作者：
Takafumi Aoki
中科院分区：
文献类型：
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作者：
Shunsuke Tatsumi;Masanori Hariyama;Koichi Ito;Takafumi Aoki
PatchMatch 多视图立体 (MVS) 是一种从多视图图像生成深度图的方法，预计可用于机器人视觉、3D 测量和 3D 重建等各种应用。 PatchMatch MVS 的主要缺点是计算量大，并且强烈希望其加速。然而，这种加速受到两个问题的阻碍。首先，虽然 PatchMatch MVS 通过在相邻像素之间传播估计结果来估计深度图，但它不适合基于 GPU 的加速。其次，由于用于立体匹配的匹配窗口的形状是动态改变的，因此读取其像素在存储器访问中效率低下。本文提出了一种有效利用片上 FIFO 的 FPGA 加速器来解决传播问题。此外，通过具有固定形状并覆盖匹配窗口的覆盖窗口来改善匹配窗口的像素读取。 FPGA加速器采用基于开放计算语言(OpenCL)的设计工具进行设计。尽管 PatchMatch MVS 的参数取决于对象图像，但这些参数可以通过基于 OpenCL 的设计轻松更改。实验结果表明，FPGA实现的处理速度分别比CPU和GPU快3.4倍和2.2倍，并且FPGA实现的功耗延迟积分别是CPU和GPU实现的3.2%和5.7%。
PatchMatch multi-view stereo (MVS) is one method generating depth maps from multi-view images and is expected to be used for various applications such as robot vision, 3D measurement, and 3D reconstruction. The major drawback of PatchMatch MVS is its large computational amount, and its acceleration is strongly desired. However, this acceleration is prevented by two problems. First, though PatchMatch MVS estimates depth maps by propagating estimation results among neighbor pixels, it is not suitable for GPU-based acceleration. Second, since the shape of a matching window used for stereo matching is changed dynamically, reading its pixels is inefficient in memory access. This paper proposes an FPGA accelerator exploiting on-chip FIFOs efficiently to solve the propagation problem. Moreover, reading pixels of a matching window is improved by a cover window which has the fixed shape and covers the matching window. The FPGA accelerator is designed using a design tool based on Open Computing Language (OpenCL). Although parameters of PatchMatch MVS depend on object images, these parameters can be changed easily by the OpenCL-based design. The experimental results demonstrate that the FPGA implementation achieves 3.4 and 2.2 times faster processing speeds than the CPU and GPU ones, respectively, and the power-delay product of the FPGA implementation is 3.2 and 5.7% of the CPU and GPU ones, respectively.