VLSI limitations from drain-induced barrier lowering
VLSI limitations from drain-induced barrier lowering
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DOI：
10.1109/jssc.1979.1051189
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发表时间：
1979-04
影响因子：
3.1
通讯作者：
Ronald R. Troutman
中科院分区：
文献类型：
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作者：
Ronald R. Troutman
漏极诱导势垒降低 (DIBL) 决定了表面扩散的最终接近程度，是 VLSI 的基本电气限制之一。使用二维数值模型研究了与 DIBL 相关的重要设计参数，并引入了一个简单的概念模型来帮助理解结果。在 IGFET 的正常工作条件下，DIBL 在源极处产生表面（而不是体）注入。基本情况与缩放设计的比较表明，简单的线性缩放本身不足以将 DIBL 保持在可容忍的量。
Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.