Introduction to Flash memory
Introduction to Flash memory
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DOI：
10.1109/jproc.2003.811702
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发表时间：
2003-04-01
影响因子：
20.6
通讯作者：
Visconti, A
中科院分区：
文献类型：
--
作者：
Bez, R;Camerlenghi, E;Visconti, A
过去十年半导体存储器领域中最相关的现象是闪存市场的爆炸式增长，这是由蜂窝电话和其他类型的电子便携式设备（掌上电脑、移动的PC、mp3音频播放器、数码相机等）驱动的。此外，在未来几年中，便携式系统将需要更多的非易失性存储器，或者具有高密度和非常高的写入吞吐量用于数据存储应用，或者具有快速随机存取用于代码执行。强大的整合技术诀窍（超过十年的经验）、灵活性和成本使闪存成为大多数非易失性存储器应用中使用率高、整合良好和成熟的技术。如今，闪存销售在整个半导体市场中占据相当大的份额。尽管过去曾提出过不同类型的闪存单元和架构，但如今其中两种可被视为行业标准：公共接地NOR闪存，由于其多功能性，可同时寻址代码和数据存储段，以及NAND闪存，本文将主要关注NOR闪存技术的发展，目的是描述迄今为止使用的存储单元的基本功能和今天整合的主要单元架构。NOR单元基本上是由沟道热电子编程并由Fowler-Nordheim隧穿擦除的浮栅MOS晶体管。主要的可靠性问题，如电荷保持和耐久性，将被讨论，以及负责的基本物理机制的理解。这些考虑因素中的大多数也适用于NAND单元，因为它基于浮栅MOS晶体管的相同概念。此外，将介绍对多电平方法的深入了解，其中两个位存储在同一单元中。事实上，在每个技术节点处利用多级方法允许增加存储器效率，几乎使密度加倍。在相同的芯片尺寸下，扩大了应用范围，降低了单位成本。最后，将讨论NoR Flash单元的缩放问题，指出主要的挑战。闪存单元的缩放已被证明是真正可能的，并能够遵循摩尔定律，直到130纳米技术的世代。技术开发和整合的专有技术预计将维持国际半导体技术路线图预测的90和65纳米技术节点的规模趋势。要解决的关键问题之一，以允许低于65纳米节点的单元缩放是隧道氧化物厚度的减少，因为隧道减薄是由内在和外在机制的限制。
The most relevant phenomenon of this past decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipment (palm top, mobile PC, mp3 audio player digital camera, and so on). Moreover in the coming years, portable systems will demand even more nonvolatile memories, either with high density and very high writing throughput for data storage application or with fast random access for code execution in place. The strong consolidated know-how (more than ten ye ars of experience), the flexibility, and the cost make the Flash memory a largely utilized, well consolidated, and mature technology for most of the nonvolatile memory applications. Today, Flash sales represent a considerable amount of the overall semiconductor market.Although in the past different types of Flash cells and architectures have been proposed, today two of them can be considered as industry standard: the common ground NOR Flash, that due to its versatility is addressing both the code and data storage segments, and the NAND Flash, optimized for the data storage market.This paper will mainly focus on the development of the NOR Flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, will be discussed, together with the understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor.Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, will be presented. In fact, the exploitation of the multilevel approach at each technology node allows the increase of the memory efficiency, almost doubling the density. at the same chip size, enlarging the application range, and reducing the cost per bit.Finally, the NoR Flash cell scaling issues will be covered, pointing out the main challenges. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore's law down to the 130-nm technology generations. The technology development and the consolidated know-how is expected to sustain the scaling trend down to the 90- and 65-nm technology nodes as forecasted by the International Technology Roadmap of Semiconductors. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.