Hierarchical Verification of Galois Field Circuits
Hierarchical Verification of Galois Field Circuits
复制标题
伽罗瓦场电路的分层验证
DOI：
10.1109/tcad.2007.895755
复制
发表时间：
2007
影响因子：
2.9
通讯作者：
D. R. Chowdhury
中科院分区：
文献类型：
--
作者：
Debdeep Mukhopadhyay;Gaurav Sengar;D. R. Chowdhury
本文提出了一种层次结构方法，用于对Galois现场体系结构电路的形式硬件验证。已经探索了降低的有序功能决策图。根据可用的资源，发现该提出的方法可在时空上带来巨大的收益。实验支持了理论主张。
This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that are available. The theoretical claims that were made have been supported by experiments.