Investigation of SOI-LDMOS for RF-Power Applications Using Computational Load Pull
Investigation of SOI-LDMOS for RF-Power Applications Using Computational Load Pull
复制标题
DOI：
10.1109/ted.2008.2011848
复制
发表时间：
2009-02
影响因子：
3.1
通讯作者：
O. Bengtsson;L. Vestling;J. Olsson
中科院分区：
文献类型：
--
作者：
O. Bengtsson;L. Vestling;J. Olsson
小信号和计算负载牵引模拟被用来研究在高功率操作的高频绝缘体上硅LDMOS晶体管的效率上的衬底电阻率的效果。研究了在不同介电常数衬底上的相同晶体管。使用计算负载牵引，他们的高功率性能进行评估。结果进行了比较，与以前的调查，关断状态的输出电阻，高效率的操作。从大信号仿真中，提取基于负载线匹配的输出电路模型，其参数可从小信号仿真中追踪。它示出，虽然高的关断状态输出电阻是一个很好的指示，它是不够的高效率在高功率操作。通过衬底的耦合的偏置和频率依赖性使得更详细的导通状态分析是必要的。结果表明，非常低的电阻率和高电阻率的SOI衬底都导致在所研究的频率和偏置点的高效率。它还表明，一个正常掺杂的介质电阻率衬底的结果在一个显着较低的效率。
Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on-insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the off-state output resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simulations. It is shown that, albeit high off-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed on-state analysis necessary. It is shown that very low resistivity and high-resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.