Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache
Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache
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DOI：
10.1109/vts.2017.7928937
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发表时间：
2017-04
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影响因子：
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通讯作者：
Nour Sayed;Fabian Oboril;R. Bishnoi;M. Tahoori
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作者：
Nour Sayed;Fabian Oboril;R. Bishnoi;M. Tahoori
自旋转移扭矩磁随机存取存储器（STT-MRAM）由于其具有非易失性、高密度、CMOS兼容性和零泄漏等各种吸引人的特性，具有成为通用存储技术的潜力。然而，与SRAM相比，STT-MRAM存在写延迟高、可靠性差的问题。这主要是由于其切换的随机性，这使得它不适合快速缓存，如L1。采用具有多比特纠错能力的鲁棒纠错编码（ECC）来优化写余量和可靠性，导致解码延迟大，校验位多。在本文中，我们提出了一种新的解决方案，以排除在解码延迟和存储开销方面使用ECC的高成本，从而能够将STT-MRAM用于快速缓存。我们利用STT-MRAM由于磁隧道结（MTJ）单元的性质而产生不对称误差的事实，这使得ECC成为解决此类误差的悲观解决方案。因此，提出采用高效的系统单向错误检测码（SEDC）来代替传统的ECC，并结合合适的缓存访问机制，在检错时获取正确的数据。与现有的解决方案相比，我们提出的方法提供了数量级更好的可靠性和相当大的性能改进，使STT-MRAM适用于快速缓存。
Spin Transfer Torque Magnatic Random Access Memory (STT-MRAM) has the potential to become a universal memory technology due to its various attractive features such as non-volatility, high density, CMOS compatibility and zero leakage. However, STT-MRAM suffers from high write latency and poor reliability compared to SRAM. This is primarily due to its stochastic nature of switching, which makes it not suitable for fast caches such as L1. The use of robust Error Correction Coding (ECC) with multiple bit correction capability to optimize the write margin and reliability results in large decoding latencies and large number of check bits. In this paper, we propose a new solution to exclude the high costs of using ECC in terms of decoding latency and storage overhead to be able to use STT-MRAM for fast caches. We exploit the fact that STT-MRAM poses asymmetric errors due to the nature of Magnetic Tunnel Junction (MTJ) cell, which makes ECC a pessimistic solution to address such errors. Therefore, efficient Systematic Unidirectional Error-Detecting Code (SEDC) is proposed to be adopted instead of conventional ECC combined with proper cache access mechanism to fetch correct data in case of error detection. Our proposed approach provides orders of magnitude better reliability and considerable performance improvement that makes STT-MRAM viable for fast-caches compared to the existing solutions.