STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing
STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing
复制标题
基于 STT-MRAM 的低功耗同步非易失性逻辑，具有定时解复用功能
DOI：
10.1145/2770287.2770295
复制
发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Y. Lian
中科院分区：
文献类型：
--
作者：
Kejie Huang;Rong Zhao;Y. Lian
超大规模集成电路（VLSI）系统中的高功耗和长互连延迟是进一步缩小工艺节点的两个主要限制。因此，新的技术和计算机体系结构正在集中发展，以减少功耗和互连延迟。磁性隧道结（MTJ）纳米柱具有非易失性、快速开关速度和高密度的优点，有望实现新的设计和架构，以显著减轻功耗和延迟问题。本文提出了基于MTJ的基本逻辑门（包括INV、（N）AND、（N）OR和XOR）的新型存储器逻辑设计。MTJ共享和定时解复用技术被用于所提出的非易失性逻辑门中，以大大降低写入功率。仿真结果表明，所设计的非易失性逻辑门的写入功率低至285 fJ/bit。基本的逻辑门可以在小于160 ps的时间内完成读操作，读能量为4.35fJ。此外，所提出的非易失性逻辑门可以在制造之后重新配置，这使得设计更加灵活和鲁棒。
The high power and long global interconnection delay are two of the major limits for further scaling down of the process nodes in the very large scale integrated (VLSI) systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents new logic-in-memory designs of the basic logic gates based on MTJs, including INV, (N)AND, (N)OR and XOR. The MTJ sharing and timing demultiplexing techniques are used in the proposed non-volatile logic gates to greatly reduce the write power. The simulation results show that the write power of the proposed non-volatile logic gates is as low as 285fJ/bit. The basic logic gates can finish the read operation in less than 160ps with 4.35f J read energy. Moreover, the proposed non-volatile logic gates may be reconfigured after fabrication, which makes the designs more flexible and robust.