An Efficient Montgomery Multiplication Algorithm and RSA Cryptographic Processor
An Efficient Montgomery Multiplication Algorithm and RSA Cryptographic Processor
复制标题
高效蒙哥马利乘法算法和RSA密码处理器
DOI：
10.1109/iccima.2007.70
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
R. Vig
中科院分区：
文献类型：
--
作者：
R. Garg;R. Vig
提出了用于实现蒙哥马利乘法算法的新的通用硅体系结构。本文提出了一种有效的Montgomery模块化乘法技术，该技术采用多位移动和随身携带的添加来执行长期算术算术。蒙哥马利乘法的数据吞吐量的增加约为45.49％（长度为1024位），而硬件减少为传统方法的24.27％。因此，相应的硬件实现在区域方面是最佳的，并为蒙哥马利乘法提供了更高的数据吞吐量。通过将其应用于具有512位和1024位密钥大小的RSA处理器架构的设计，可以证明这种方法的实际应用。 RSA处理器还提供更高的吞吐量（1024位），面积略有增加（22.4％）。这种优化也与技术无关，因此不仅应该适合FPGA实施，而且应适合ASIC。蒙哥马利设计和RSA处理器已在Xilinx virtex-4系列上进行了512、1024和2048的实际位长度评估。所得的蒙哥马利乘数和RSA处理器性能结果在迄今为止在文献中迄今为止最快报道的最快。
New, generic silicon architecture for implementing Montgomery's multiplication algorithm is presented. This paper proposes an efficient Montgomery modular multiplication technique that employs multi-bit shifting and carry-save addition to perform long-integer arithmetic. The gain in data throughput for Montgomery multiplication is approximately 45.49% (for 1024-bit length) and the hardware reduction is 24.27% of the traditional methods. Hence, the corresponding hardware realization is optimal in terms of area and offer higher data throughput for Montgomery multiplication. The practical application of this approach has been demonstrated by applying this to the design of RSA processor architecture with 512-bit and 1024-bit key size. The RSA processor also offers higher throughput (32.18% for 1024-bit) with a slight increase in area (22.4%). This optimization is also technology independent and thus should suit well not only FPGA implementation but also ASIC. The Montgomery design and RSA processor has been evaluated on Xilinx Virtex-4 series for the practical bit lengths of 512, 1024 and 2048. The resulting Montgomery multiplier and the RSA processor performance results presented at the fastest reported to date in literature.