A Monolithic Hardware Implementation of Kyber: Comparing Apples to Apples in PQC Candidates
A Monolithic Hardware Implementation of Kyber: Comparing Apples to Apples in PQC Candidates
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DOI：
10.1007/978-3-030-88238-9_6
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
Mojtaba Bisheh-Niasar;R. Azarderakhsh;Mehran Mozaffari Kermani
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文献类型：
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作者：
Mojtaba Bisheh-Niasar;R. Azarderakhsh;Mehran Mozaffari Kermani
随着大规模量子计算机的出现，因式分解和离散对数问题可以使用多项式时间量子算法来解决。为了确保公钥安全，需要过渡到抗量子密码协议。针对不同平台和不同应用目标的硬件加速器的性能在PQC候选人的差异化中起着重要作用。基于FPGA和ASIC的硬件加速器还提供了更高的灵活性，可以以极低的面积或超高的性能实现另一种高成本。虽然PQC方案的硬件/软件协同设计开发已经得到了越来越多的研究工作，有效的纯硬件实现的成本分析仍然缺乏。另一方面，由于FPGA具有各种类型的硬件资源，因此评估并对基于硬件的实现进行准确和公平的比较是非常具有挑战性的。没有共同的基础，苹果就被比作橘子。本文展示了Kyber作为NIST后量子密码标准化过程第三轮决赛选手之一的纯硬件架构。为了使真实的，现实的，和可比较的评估在PQC计划的硬件平台，我们比较我们的架构在ASIC平台作为一个共同的基础，它优于以前的作品在文献中。
With the advent of large-scale quantum computers, factoring and discrete logarithm problems could be solved using the polynomial-time quantum algorithms. To ensure public-key security, a transition to quantum-resistant cryptographic protocols is required. Performance of hardware accelerators targeting different platforms and diverse application goals plays an important role in PQC candidates’ differentiation. Hardware accelerators based on FPGAs and ASICs also provide higher flexibility to create a very low area or ultra-high performance implementations at the high cost of the other. While the hardware/software co-design development of PQC schemes has already received an increasing research effort, a cost analysis of efficient pure hardware implementation is still lacking. On the other hand, since FPGA has various types of hardware resources, evaluating and making the accurate and fair comparison of hardware-based implementations against each other is very challenging. Without a common foundation, apples are compared to oranges. This paper demonstrates a pure hardware architecture for Kyber as one of the finalists in the third round of the NIST post-quantum cryptography standardization process. To enable real, realistic, and comparable evaluations in PQC schemes over hardware platforms, we compare our architecture over the ASIC platform as a common foundation showing that it outperforms the previous works in the literature.