Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires
Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires
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DOI：
10.1109/led.2009.2021079
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发表时间：
2009-07-01
影响因子：
4.9
通讯作者：
Kwong, D. -L.
中科院分区：
文献类型：
--
作者：
Chen, Z. X.;Yu, H. Y.;Kwong, D. -L.
这封信演示了一个垂直硅纳米线（SiNW）为基础的隧道场效应晶体管（TFET）使用CMOS兼容技术。采用Si p（+）-i-n（+）隧穿结，栅长约为200 nm的TFET表现出约70 mV/dec的良好亚阈值摆幅，约17 mV/V的上级漏致势垒降低，以及约10（7）的优良I-on-I-off比和低I-off（约7 pA/μ m）。所获得的53 μ A/μ m的I-on可以进一步增强与异质结在隧道界面。垂直SiNW基TFET被认为是超低功耗和高密度应用的理想选择。
This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p(+)-i-n(+) tunneling junction, the TFET with a gate length of similar to 200 nm exhibits good subthreshold swing of similar to 70 mV/dec, superior drain-induced-barrier-lowering of similar to 17 mV/V, and excellent I-on-I-off ratio of similar to 10(7) with a low I-off (similar to 7 pA/mu m). The obtained 53 mu A/mu m I-on can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.