Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors
Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors
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DOI：
10.1109/23.173239
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发表时间：
1992-10
影响因子：
1.8
通讯作者：
Jr. Leonard R. Rockett
中科院分区：
文献类型：
--
作者：
Jr. Leonard R. Rockett
研究了门控电阻作为一种创新技术用于硬化定标静态随机存取存储器(SRAM)设计。门控电阻是有源时钟多晶硅电阻，用于提供单粒子翻转(SEU)硬度。它们被放置在SRAM单元的交叉耦合段中，类似于使用无源多晶硅电阻器的设计。门控电阻的高阻断状态保护存储的单元数据不受SEUS的影响。然而，在写入单元周期期间，通过字线时钟信号将选通电阻计时到低电阻导通状态。由此产生的低阻电流路径降低了内部单元节点的充电时间常数，从而保持了对单元的快速写入响应。门控电阻技术的实验研究证明了其处理能力和器件的可行性。研究发现，门控电阻工艺很容易集成到抗辐射半微米工艺中，不会引入任何工艺复杂性，也不会对功能成品率产生负面影响，也不会降低总剂量硬度。>；
The use of gated resistors as an innovative technique for hardening scaled static RAM (SRAM) designs is examined. Gated resistors are actively clocked polysilicon resistors that are used to provide single-event upset (SEU) hardness. they are placed in the cross-coupled segments of SRAM cells, similar to designs using passive polysilicon resistors. The high-resistance OFF-state of the gated resistors protects the stored cell data from SEUs. However, during write-cell cycles, the gated resistors are clocked into a low-resistance ON-state by a wordline clock signal. The resultant low-resistance current paths reduce the charging time constants of the internal cell nodes, thus preserving the fast write response to the cell. Experimental investigations of gated resistor technology demonstrated the processing capability and device feasibility. The gated resistor process was found to be easy to integrate into a radiation-hardened half-micrometer CMOS process without introducing any process complexities and without negatively affecting functional yield or degrading total dose hardness. >