Single-event upset and snapback in silicon-on-insulator devices and integrated circuits
Single-event upset and snapback in silicon-on-insulator devices and integrated circuits
复制标题
绝缘体上硅器件和集成电路中的单粒子翻转和骤回
DOI:
10.1109/23.903749
复制
发表时间:
2000
影响因子:
1.8
通讯作者:
P. Winokur
中科院分区:
文献类型:
--
作者:
P. Dodd;M. Shaneyfelt;D. Walsh;J. Schwank;G. L. Hash;R. A. Loemker;B. Draper;P. Winokur
The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.