Instruction Extension of RV32I and GCC Back End for Ascon Lightweight Cryptography Algorithm
Instruction Extension of RV32I and GCC Back End for Ascon Lightweight Cryptography Algorithm
复制标题
Ascon轻量级密码算法的RV32I和GCC后端指令扩展
DOI：
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
Berna Örs
中科院分区：
文献类型：
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作者：
Özlem Altınay;Berna Örs
轻量级密码技术可以在资源受限的嵌入式设备中提供安全性和隐私性。延迟和内存消耗是轻量级密码算法实现的性能指标中的关键元素。Ascon轻量级密码算法是CEASAR竞赛的决赛选手之一。在这项研究中，已经开发了特殊的加密非标准RISC-V指令，以减少在基于RV 32 I的处理器上执行算法所需的时钟周期和指令存储器的数量。已经开发了一种分析方法来选择最佳的特殊指令，以实现最高的性能效益。针对RISC-V处理器的特殊密码指令扩展，通过扩展GNU编译器集合和Spike RISC-V伊萨模拟器，形成了一个端到端的测试环境。新指令的新内在函数和指令模式已集成到GCC RISC-V后端中。斯派克已经用新的指令修改了运行程序。该算法已被分析与建议的指令和不同的优化标志和改进的结果已在这项研究中示出。
Lightweight cryptography is useful to provide security and privacy in resource constraint embedded devices. Latency and memory consumption are the key elements in performance metrics for lightweight cryptography algorithm implementations. Ascon lightweight cryptography algorithm is one of the finalists in CEASAR competition. In this study, special cryptographic non-standard RISC-V instructions have been developed in order to reduce the required number of clock cycles and instruction memory for the execution of the algorithm on RV32I based processors. A profiling methodology has been developed to choose the best special instruction for achieving the highest benefit in performance. An end-to-end test environment has been formed by extending the GNU Compiler Collection and Spike RISC-V ISA Simulator for the special cryptographic instruction extensions of RISC-V processors. New intrinsic functions and instruction patterns for the new instructions have been integrated into the GCC RISC-V back end. Spike has been modified with the new instructions to run the program. The algorithm has been analysed with the proposed instructions and different optimization flags and improvement results have been shown in this study.