Pattern-directed circuit virtual partitioning for test power reduction
Pattern-directed circuit virtual partitioning for test power reduction
复制标题
DOI：
10.1109/test.2007.4437633
复制
发表时间：
2007-10
期刊：
影响因子：
--
通讯作者：
Qiang Xu;D. Hu;D. Xiang
中科院分区：
文献类型：
--
作者：
Qiang Xu;D. Hu;D. Xiang
对于正在测试的大电路（切割），某些测试模式可能会导致超过切口的功率等级的过度耗能。设计人员可以诉诸于低功率自动测试模式生成（ATPG）工具来解决此问题，但是，即使有可用的工具，这通常会导致更大的测试数据量，并且需要额外的计算工作。另一种方法是将电路划分为多个子电路并分别测试。不幸的是，这通常涉及每个分区子电路的耗时的ATPG，并解决如何实现子电路之间胶水逻辑的可接受故障覆盖率的问题。在本文中，我们提出了一种新型的低功率虚拟测试分区技术，而没有上述缺点。基本思想是以这样的方式分配电路，以使子电路之间的胶水逻辑中的故障可以通过在整个电路级别上应用的模式来检测到，而具有较高功率耗散的模式可以应用于整个电路级别上。分区的子电路而不会损失故障覆盖。在分区过程中还考虑了扫描链路由成本。实验结果表明，该提出的技术在降低测试能力方面非常有效。
For a large circuit under test (CUT), it is likely that some test patterns result in excessive power dissipations that exceed the CUT's power rating. Designers may resort to low-power automatic test pattern generation (ATPG) tools to solve this problem, which, however, usually leads to larger test data volume and requires extra computational effort, even if such tools are available. Another method is to partition the circuit into multiple subcircuits and test them separately. Unfortunately, this usually involves rerunning the time-consuming ATPG for each partitioned subcircuit and solving the problem of how to achieve an acceptable fault coverage for the glue logic between subcircuits. In this paper, we propose a novel low-power virtual test partitioning technique without the above-mentioned shortcomings. The basic idea is to partition the circuit in such way that the faults in the glue logic between subcircuits can be detected by patterns with low power dissipation that are applied at the entire circuit level, while the patterns with high power dissipation can be applied within a partitioned subcircuit without loss of fault coverage. Scan chain routing cost has also been considered during the partitioning process. Experimental results show that the proposed technique is very effective in reducing test power.