Realization of multiple valued logic and memory by hybrid SETMOS architecture
Realization of multiple valued logic and memory by hybrid SETMOS architecture
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DOI：
10.1109/tnano.2005.858602
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发表时间：
2005-11
影响因子：
2.4
通讯作者：
Santanu Mahapatra;A. M. Ionescu
中科院分区：
文献类型：
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作者：
Santanu Mahapatra;A. M. Ionescu
提出了一种新型的互补型金属氧化物半导体（CMOS）单电子晶体管（SET）混合结构SETMOS，该结构在比传统SET高得多的电流水平下提供库仑阻塞振荡和准周期负微分电阻效应。利用库仑阻塞振荡特性实现多值字门，利用周期性负微分电阻特性实现无电容多值静态随机存取存储器（MVSRAM）单元。SETMOS字面值门然后用于构建其他MV逻辑构建块，例如，传输门、二进制到MV逻辑编码器和MV到二进制逻辑解码器。分析SET模型模拟，以验证所提出的MV逻辑和存储器单元的四元逻辑系统的功能。SETMOS MV架构被发现是更快，更少的温度敏感性比以前报道的混合CMOS SET为基础的MV电路。
A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.